This was my final project for my graduate ECE-564 course. The project uses hardware to process matrix multiplication such as how neural networks operate. I designed a very cost-effective and low area utilization using the Verilog hardware descriptive language. I then later synthesized the design using a program called Synopsys. This modeled the performance and efficiency of my design, and also allowed for estimation of manufacturing costs.
The project in its entirety can be found in the Git repository below.
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https://git.robsengineeringadventures.com/rmhunter/bit-fusion